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| 74VHC4040 12-Stage Binary Counter May 2007 74VHC4040 12-Stage Binary Counter Features High speed; fMAX = 210MHz at VCC = 5V Low power dissipation: ICC = 4A (Max.) at TA = 25C High noise immunity: VNIH = VNIL = 28% VCC (Min.) Power down protection is provided on all inputs Wide operating voltage range: VCC (Opr.) = 2V - 5.5V Low noise: VOLP = 0.8V (Max.) Pin and function compatible with 74HC4040 tm General Description The VHC4040 is an advanced high-speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The VHC4040 is a 12-stage counter which increments on the negative edge of the input clock and all outputs are reset to a low level by applying a logical high on the reset input. An input protection circuit insures that 0V to 7V can be applied to the inputs without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Ordering Information Order Number 74VHC4040M 74VHC4040MTC Package Number M16A MTC16 Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering number. Connection Diagram Pin Descriptions Pin Names Q0-Q11 CP MR Description Flip-Flop Outputs Negative Edged Triggered Clock Master Reset (c)1993 Fairchild Semiconductor Corporation 74VHC4040 Rev. 1.3 www.fairchildsemi.com 74VHC4040 12-Stage Binary Counter Logic Symbols IEEE/IEC Logic Diagram (c)1993 Fairchild Semiconductor Corporation 74VHC4040 Rev. 1.3 www.fairchildsemi.com 2 74VHC4040 12-Stage Binary Counter Timing Diagram (c)1993 Fairchild Semiconductor Corporation 74VHC4040 Rev. 1.3 www.fairchildsemi.com 3 74VHC4040 12-Stage Binary Counter Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC VIN VOUT IIK IOK IOUT ICC TSTG TL Supply Voltage DC Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current DC VCC / GND Current Storage Temperature Parameter Rating -0.5V to +7.0V -0.5V to +7.0V -0.5V to VCC + 0.5V -20mA 20mA 25mA 75mA -65C to +150C 260C Lead Temperature (Soldering, 10 seconds) Recommended Operating Conditions(1) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC VIN VOUT TOPR t r, t f Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time VCC = 3.3V 0.3V VCC = 5.0V 0.5V Parameter Rating 2.0V to +5.5V 0V to +5.5V 0V to VCC -40C to +85C 0 100ns/V 0 20ns/V Note: 1. Unused inputs must be held HIGH or LOW. They may not float. (c)1993 Fairchild Semiconductor Corporation 74VHC4040 Rev. 1.3 www.fairchildsemi.com 4 74VHC4040 12-Stage Binary Counter DC Electrical Characteristics TA = 25C Symbol VIH VIL VOH TA = -40C to +85C Max. Min. 1.50 0.7 x VCC 0.50 0.50 0.3 x VCC 1.9 2.9 4.4 2.48 3.80 V V Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage VCC (V) 2.0 3.0 - 5.5 2.0 3.0 - 5.5 2.0 3.0 4.5 3.0 4.5 Conditions Min. 1.50 0.7 x VCC Typ. Max. Units V 0.3 x VCC VIN = VIH or VIL IOH = -50A 1.9 2.9 4.4 IOH = -4mA IOH = -8mA VIN = VIH or VIL IOL = 50A 2.58 3.94 0.0 0.0 0.0 IOL = 4mA IOL = 8mA VIN = 5.5V or GND VIN = VCC or GND 0.1 0.1 0.1 0.36 0.36 0.1 4.0 2.0 3.0 4.5 VOL LOW Level Output Voltage 2.0 3.0 4.5 3.0 4.5 0.1 0.1 0.1 0.44 0.44 1.0 40.0 V IIN ICC Input Leakage Current Quiescent Supply Current 0 - 5.5 5.5 A A (c)1993 Fairchild Semiconductor Corporation 74VHC4040 Rev. 1.3 www.fairchildsemi.com 5 74VHC4040 12-Stage Binary Counter AC Electrical Characteristics TA = +25C Symbol tPLH, tPHL TA = -40C to +85C Min. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 75 50 125 80 10 10 pF pF MHz Parameter Propagation Delay Time to Q1 VCC (V) 3.3 0.3 5.0 0.5 Conditions CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF Min. Typ. 7.5 10.0 4.8 6.3 2.4 1.6 8.3 10.8 5.6 7.1 Max. 11.9 15.4 7.3 9.3 4.4 3.1 12.8 16.3 8.6 10.6 Max. Units 14.0 17.5 8.5 10.5 ns 5.0 ns 3.5 15.0 18.5 10.0 12.0 MHz ns ns ns ns tPLH, tPHL Propagation Delay Time between Stages from Qn to Qn+1 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF VCC (2) = Open 90 55 150 95 tPHL Propagation Delay Time MR-Qn fMAX Maximum Clock Frequency 3.3 0.3 5.0 0.5 140 80 210 125 4 21 CIN CPD Input Capacitance Power Dissipation Capacitance Note: 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (Opr.) = CPD * VCC * fN + ICC AC Operating Requirements TA = 25C Symbol tw(L), tw(H) tw(L) tREC TA = -40C to +85C Units ns ns ns 5.0 5.0 5.0 5.0 5.0 5.0 Parameter Minimum Pulse Width (CP) Minimum Pulse Width (MR) Minimum Removal Time (MR) VCC (V) 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 Typ. Guaranteed Minimum 5.0 5.0 5.0 5.0 5.0 5.0 (c)1993 Fairchild Semiconductor Corporation 74VHC4040 Rev. 1.3 www.fairchildsemi.com 6 74VHC4040 12-Stage Binary Counter Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 1. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A (c)1993 Fairchild Semiconductor Corporation 74VHC4040 Rev. 1.3 www.fairchildsemi.com 7 74VHC4040 12-Stage Binary Counter Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. 5.000.10 4.55 5.90 4.45 7.35 0.65 4.40.1 1.45 5.00 0.11 12 MTC16rev4 Figure 2. 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 (c)1993 Fairchild Semiconductor Corporation 74VHC4040 Rev. 1.3 www.fairchildsemi.com 8 74VHC4040 12-Stage Binary Counter TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx Across the board. Around the world.TM ActiveArrayTM BottomlessTM Build it NowTM CoolFETTM CorePLUSTM CROSSVOLTTM CTLTM Current Transfer LogicTM DOMETM 2 E CMOSTM (R) EcoSPARK EnSignaTM FACT Quiet SeriesTM (R) FACT (R) FAST FASTrTM FPSTM (R) FRFET GlobalOptoisolatorTM GTOTM (R) HiSeCTM i-LoTM ImpliedDisconnectTM IntelliMAXTM ISOPLANARTM MICROCOUPLERTM MicroPakTM MICROWIRETM Motion-SPMTM MSXTM MSXProTM OCXTM OCXProTM (R) OPTOLOGIC (R) OPTOPLANAR PACMANTM PDP-SPMTM POPTM (R) Power220 (R) Power247 PowerEdgeTM PowerSaverTM Power-SPMTM (R) PowerTrench Programmable Active DroopTM (R) QFET QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM ScalarPumpTM SMART STARTTM (R) SPM STEALTHTM SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TCMTM (R) The Power Franchise TM TinyBuckTM (R) TinyLogic TINYOPTOTM TinyPowerTM TinyWireTM TruTranslationTM SerDesTM (R) UHC UniFETTM VCXTM WireTM TinyBoostTM DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD'S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Preliminary Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I27 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. No Identification Needed Full Production Obsolete Not In Production (c)1993 Fairchild Semiconductor Corporation 74VHC4040 Rev. 1.3 www.fairchildsemi.com 9 |
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